Super junction structure may reduce the product of on-state resistance Ron and area A. Therefore the utilization of super junction structures could shrink the scale of semiconductor devices. By reducing the width of the P-type pillar or N-type pillar in a super junction structure, the on-state resistance Ron may be further decreased. When this device scale-down scheme is applied in planar metal oxide semiconductor field effect transistor (MOSFET) device, the scale of poly gate needs to be shrunk simultaneously. Thus, in planar MOSFET device, the utilization of super junction structure may also lower down the product of Ron and Qg (gate charge), and further lower down the power consumption of the gate driver circuit.
However, if the super junction structure is applied in trench-gate MOSFET, the gate charge Qg does not decrease when the width of pillar decreases. This is because the scale of the trench gate structure is not changed with the width of the pillar. As a result, a technology that could lower down the product of Ron and Qg (Ron×Qg) is desired.